1. Field of the Invention
The present invention relates to an optical and X-ray lithography technology in manufacture of a semiconductor integrated circuit, a liquid crystal panel or the like, and more particularly to a verification method (lithography simulation) of a semiconductor integrated circuit, a verification program thereof, and a manufacturing method of a semiconductor device.
2. Description of the Related Art
In recent years, as a semiconductor integrated circuit manufacturing technology has been sophisticated and a difficulty level has been increased, it is becoming very hard to increase a process yield (a ratio of non-defective chips per wafer), and a critical pattern exists even if design rules are kept, resulting in a decrease in a process yield. Therefore, in order to increase a process yield, it has begun to attach importance to performing lithography simulation with respect to a design layout pattern before making a mask to reduce hot spots (critical patterns).
For example, Jpn. Pat. Appln. KOKAI Publication No. 2003-92237 provides means for setting semiconductor process conditions and mask pattern shapes avoiding occurrence of crystal defects based on simulation and setting robust semiconductor process conditions with respect to unevenness or fluctuations in semiconductor manufacturing process conditions or unevenness in mask pattern shapes.
However, a recent lithography verification tool takes the same amount of time as an optical proximity correction (OPC) processing time even under one set of conditions, and cannot feed back an error result to a design layout in a realistic turnaround time (TAT).
Therefore, there has been demanded realization of a semiconductor integrated circuit pattern verification method which can shorten a turnaround time, a program which allows a computer to execute this method, and a manufacturing method of a semiconductor device which realizes a pattern verified by this method and program on a semiconductor substrate.